The present invention relates to a lithography verification apparatus suitable for a model of a semiconductor integrated circuit.
A lithography process has been known as a general semiconductor manufacturing technology. This lithography process optically transfers a predetermined mask pattern to a wafer using an exposure device.
With a recent demand for miniaturization, mask patterns have been fabricated in consideration of an optical proximity correction (OPC and hereinafter also called “OPC”) and resolution enhancement techniques (RET). That is, in the process of circuit layout design and OPC development, it is determined whether errors (typically an excess of an error standard value, etc.) expected to be problematic in manufacture, based on simulation exist in a desired circuit layout, or an improved one of the original circuit layout shape, or each mask pattern obtained as a result of further execution of the OPC or the like thereon. A technique called lithography verification has been put into practical use as one for verifying and determining whether a problem occurs in any position (coordinates X and y) of such mask patterns (refer to Patent Documents 1 and 2).
As for the lithography verification, various applications such as its utilization for the OPC development and design phase, so-called DFM (Design For Manufacturability), etc. are known. However, in order to enhance the degree of completion of OPC specs or an OPC tool at the OPC development, there are principally two aims: a software defect detection for detecting defects in these software, and a mask fabrication pass/fail decision for detecting an OPC result and a design layout to be problematic in terms of a device operation/yield. In particular, the mask fabrication go/no-go decision gets involved in product deadline, the operation of each product and reliability and is further important even for an estimation of development effects.
Mask patterns have been required to be corrected based on the result of the lithography verification in such a manner that a finished shape on a wafer is brought to a desired shape, i.e., a shape intended in design. In addition to this, however, there is a need to perform their corrections under various constraints such as constraints on mask fabrication, constraints on lithography process margins.